Semiconductor fins are widely used in advanced semiconductor manufacturing technology because of the increased integration levels they provide. For example, when transistor devices such as FinFET, fin Field Effect Transistor, devices are formed they provide a gate width that may be larger, by an order of magnitude, than the gate width of the transistor formed on the same substrate section in which the semiconductor fin is formed because the gate extends over the top and sides of the fins, all of which serve as channels. Semiconductor fins have high aspect ratios and require advanced and dedicated processing operations to forming working FinFET or other devices using the semiconductor fins.
When these devices are formed using advanced processing technology and miniaturized features of increasingly small dimensions, particular care must be taken in forming the features. It is critical to ensure that the correct dimensions are achieved and that the structures are accurately positioned. It is also critical to ensure that dopant impurities are accurately introduced into particular desired locations so that they do not extend past their desired boundaries where they may undesirably overlap and/or cross-contaminate other features which may destroy device functionality. In particular, it is particularly important to ensure that the impurities introduced by ion implantation or other processes are accurately introduced into the exact locations where they are needed.
It is also desirable to economize the number of processing operations needed to produce a semiconductor device. When fewer processing operations are used, the cost to produce a device is reduced and the number of opportunities to misprocess a substrate is also reduced. It is further desirable to produce the semiconductor devices using robust materials that are not subject to attack and degradation during subsequent processing operations.
One shortcoming associated with the desire to achieve the aforementioned goals of increased integration in the formation of semiconductor fin devices, is illustrated in FIGS. 1(A)-1(F) which illustrate a prior art processing sequence. FIG. 1(A) shows semiconductor fin 3 formed over substrate 1. It should be noted that semiconductor fin 3 is viewed along a longitudinal cross-section and that gate structure 5 extends over the respective sides of the fins, and in- and out-of the plane of the figures. Gate structure 5 is formed over surface 7 of semiconductor fin 3. Gate structure 5 includes a high-k gate dielectric material and a metal gate layer formed essentially at interface 9 but not visible in FIG. 1(A). Over these interfacial features are polysilicon 11 and hardmask 13. In order to protect the high-k gate dielectric material and the metal gate formed at interface 9, seal spacers 17 are formed along the sidewalls of gate structure 5. Seal spacers 17 are shown in FIG. 1(B) and may be formed of nitride, using conventional CVD, chemical vapor deposition, processing. Seal spacers 17 formed of conventional nitride materials are subject to attack and may be removed using a conventional solution of phosphoric acid, H3PO4.
After seal spacers 17 are formed to a sufficiently wide width to protect the metal gate and high-k dielectric at interface 9, an implantation process is carried out as shown in FIG. 1(C). Arrows 19 indicate the acceleration of particles being implanted into semiconductor fin 3 and other semiconductor portions 21. The implantation process carried out may be an LDD, lightly doped drain, implantation process or a PKT, packet implantation process, or both. The implant operation damages unprotected surface 7 of semiconductor fin 3 as indicated by damaged portions 23. The implantation process may advantageously utilize an angled implant so that the damaged portions 23 may also occur on the sides of the semiconductor fins (not shown).
FIG. 1(D) shows the structure after dummy spacers 27 have additionally been formed using deposition and anisotropic etching processes. Dummy spacers 27 are typically formed of an oxide layer and a nitride layer and are used to define the area upon which epitaxial silicon formation will take place. Due to the damage of the semiconductor surface as indicated in FIG. 1(C), surface 7 is attacked and receded during the formation of dummy spacers 27, particularly during the etching portion of the process used to form dummy spacers 27, and this attack results in recessed portions 31 which generally represent loss of the semiconductor material.
FIG. 1(E) shows the structure of FIG. 1(D) after epitaxial silicon growth has been carried out. Epitaxial silicon 33 is formed on exposed silicon surfaces with dummy spacers 27 necessarily intact as their removal would also undesirably remove or at least attack conventional seal spacers 17. It may then be desired to carry out a source/drain implant with critical dimensions that are different than the CD's of the dummy spacers 27 that were used to determine the bounds of the epitaxial silicon formation process. When dummy spacers 27 are removed such as shown in FIG. 1(F), and such as may be done prior to the formation of MSW's, major sidewall spacers used to define source/drain areas, a large gap 37 undesirably results between the epitaxially grown silicon 33, and gate structure 5.
It can be seen that the limitations of conventional processing cause the damage and recession of the semiconductor fin material and necessitate the use of wide dummy spacers which result in additional shortcomings such as gap 37.
It would therefore be desirable to produce FinFET and other semiconductor fin devices that are not prone to the problems associated with the shortcomings of conventional technology.